Synopsys has introduced a full IP portfolio for TSMC’s N6C and N4C cost‑optimized process nodes. Built on silicon‑proven IP from N6 and N4P, the new portfolio targets cloud, edge, and physical AI applications, helping chip teams reduce design risk and mass‑production cost while maintaining performance and power efficiency.

The three AI compute markets (cloud, edge, physical) are expected to grow from $267B in 2025 to over $1.3T by 2030. The new IP suite covers high‑speed interfaces (PCIe, USB, Die‑to‑Die, DDR5, LPDDR6, MIPI, UFS, HDMI, DisplayPort) and foundation IP (logic libraries, memory, NVM, I/O, SLM).

Yao Yao, Synopsys VP and China president, said the portfolio enables customers to quickly launch innovative, cost‑sensitive AI devices. Chen Ping, TSMC China VP, noted that the compact N6C/N4C nodes retain power/performance advantages while simplifying architectures for physical AI.

ICgoodFind: Synopsys and TSMC team up to lower the barrier for mass‑producing edge and physical AI chips with optimized interface and foundation IP.